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| DS3112RD DS3/E3 Multiplexer Reference Design www.maxim-ic.com GENERAL DESCRIPTION The DS3112RD is a reference design for the DS3112 DS3/E3 framer/mux and the DS3150 DS3/E3 LIU. Both devices are surface-mounted to minimize board size and to provide signal integrity. Interface to the DK101/DK2000 and included software give pointand-click access to configuration and status registers from a personal computer. LEDs on the board indicate loss-of-signal, transmit driver monitor, and PRBS sync status of the LIU. The board provides BNC connectors for an external clock, the line-side transmit and receive differential pairs, and a connector for data path interface. A PLD provides registered access to the LIU control pins along with control of clock and data paths. FEATURES Soldered DS3150 and DS3112 BNC Connectors, Transformers, and Termination Passives for LIU Careful Layout for Analog Signal Paths DK2000 Interface Provides External Data Path Memory-Mapped PLD for Control of DS3150 BNC Connectors for External Clock and Line-Side Interface DK101/DK2000 Interface and Included Software Provide Point-and-Click Access to the DS3112 Register Set LEDs for Loss-of-Signal, Transmit Driver Monitor, and PRBS Sync REFERENCE DESIGN CONTENTS DS3112RD Board CD-ROM WINT1E1 Software DS3112RD.def Definition File DS3112.def Definition File DS3112RD Data Sheet DS3112 Data Sheet DS3150 Data Sheet ORDERING INFORMATION PART DS3112RD DESCRIPTION DS3112 Reference Design 1 of 11 REV: 060303 DS3112RD DS3/E3 Multiplexer Reference Design COMPONENT LIST DESIGNATION C1-C16, C20-C27 C17-C19 C28-C30 DS1-DS4 J1, J2 J3 J4-J6 J7 R1-R4, R8, R14, R500 R5, R10 R6, R7, R9, R11-R13 R501 T1, T2 TP1-TP17 U1 U2 U3 U4 U5 QTY 24 3 3 4 2 1 3 1 7 2 6 1 2 17 1 1 1 1 1 DESCRIPTION 0.1mF 10%, 25V ceramic capacitors (1206) 0.047mF 10%, 50V ceramic capacitors (1206) 10mF 20%, 16V tantalum capacitors (B case) LED, red, SMD 5-pin, right-angle, BNC connectors 5-pin, vertical, BNC connector 50-pin jumper, dual row 10-pin, dual row, vertical connector 10kW 1%, 1/8W resistors (1206) 0W 5%, 1/8W resistors (1206) 330W 0.1%, 1/10W MF resistors (0805) 75W 5%, 1/8W resistor (1206) XFMR, 1-to-2 count, 6-pin SMT Testpoint, 1 plated thru-hole T3/E3 mux/framer T3/E3/STS-1 line interface IC, hex interverter, SO IC, PLD, 100-pin TQFP IC, MUX, quad 2INPUT SUPPLIER Panasonic Panasonic Panasonic Panasonic Trompeter Cambridge Samtec Digi-Key Panasonic Panasonic Panasonic Panasonic Pulse Engineering NA Dallas Semiconductor Dallas Semiconductor Toshiba Altera Philips PART ECJ-3VB1E104K ECU-V1H473KBW ECS-T1CX106R LN1251C UCBJR220 CP-BNCPC-004 TFM-125-02-S-D-LC S2012-05-ND ERJ-8ENF1002V ERJ-8GEYJ0R00V ERA-6YEB331V ERJ-8GEYJ750V PE-65968 NA DS3112 DS3150T TC74HC04AFN EPM7128AETC100-10 74LVC157APW DH BOARD FLOORPLAN Rx TRANSFORMER LED DS3150 Tx BNC Tx TRANSFORMER Dallas Semiconductor JTAG Rx BNC DS3112 EXT CLOCK PLD LED LED LED 2 of 11 DS3112RD DS3/E3 Multiplexer Reference Design PLD MEMORY MAP The PLD on the DS3112RD is used to route clocks from the processor board DK2000/DK101 and to control the DS3150 and the DS3112. The PLD is mapped at address 00h and contains 25 registers. The first eight registers (excluding register address 01h, which has no function on the 3112RD) are read-only, and are programmed at the factory to document board identification and revision information. The next 16 registers control the state of pins on the DS3150 and DS3112. The last register controls the clock source to the FTCLK pin on the DS3112 and the MCLK pin on the DS3150. The PLD provides tri-state control of the pins. If a 01h is written to a register, the corresponding pin is forced high, a value of 00h forces the pin low, and writing any other value puts the pin in a tristate mode. The bit descriptions in the definition file for the DS3112RD describe how to control a pin specifically (Table 1). For more information about definition files, refer to the DK101/DK2000 data sheets. MEMORY MAP The DS3112 is mapped at 1000h. Table 1. DS3112RD CPLD Register Map OFFSET 0X0000 0X0002 0X0003 0X0004 0X0005 0X0006 0X0007 0X0011 0X0012 0X0013 0X0014 0X0015 0X0016 0X0017 0X0018 0X0019 0X001A 0X001B 0X001C 0X001D 0X001E 0X001F 0X0020 0X0021 NAME BID XBIDH XBIDM XBIDL BREV AREV PREV TDS0 TDS1 EFE ICE LBKS RMON TESS TTS ZCSE LBO RST MUXSEL G747E T3E3MS FRMECU FTMEI T3E3CLK TYPE Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Write Read-Write Read-Write Read-Write Read-Write Read-Write Read-Write Read-Write Read-Write Read-Write Read-Write Read-Write Read-Write Read-Write Read-Write Read-Write Read-Write DEFAULT VALUE 0x0D 0x00 0x00 0x01 -- -- -- 0x00 0x00 0x01 0x00 0x01 0x00 0x01 0x01 0x00 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x01 DESCRIPTION Board ID High Nibble Extended Board ID Middle Nibble Extended Board ID Low Nibble Extended Board ID Board FAB Revision Board Assembly Revision PLD Revision DS3150 Transmit Data Select 0 DS3150 Transmit Data Select 1 DS3150 Enhanced Feature Enable DS3150 Invert Clock Enable DS3150 Loopback Select DS3150 Receive Monitor Mode DS3150 T3/E3/STS-1 Select DS3150 Transmit Tri-State DS3150 Zero Code Suppression DS3150 Line Build-Out DS3112 Reset DS3112RD Data Path Mux DS3112 G747 Mode Enable DS3112 T3/E3 Mode Select DS3112 Error Counter Strobe DS3112 Error Insert Strobe DS3112RD Clock Select 3 of 11 DS3112RD DS3/E3 Multiplexer Reference Design LINE-SIDE CONNECTIONS The DS3112RD implements the transmit (Tx) and receive (Rx) line interface networks recommended in the DS3150 data sheet (Figure 1). The BNC connectors are labeled J1 (Tx) and J2 (Rx). Figure 1. Line-Side Circuitry TRANSMIT LIU TXP 0.05mF 330W (1%) TXN 1:2ct RECEIVE DS3150 RXP 0.05mF 330W (1%) RXN 1:2ct INTERFACE CONNECTOR Two 50-pin connectors (J4, J5) on the bottom of the board provide the processor interface, clocks, power supply, and a high-speed TDM connection supplied by the DK2000/DK101. The third connector (J6) is provided for future expansion on the DK2000 and is not connected on the DS3112RD. CONNECTING TO A COMPUTER Refer to the DK101 and DK2000 data sheets for information. BASIC OPERATION The DS3112RD powers up in the T3 mode, transmitting all ones determined by the default values in the CPLD registers (Table 1) and the DS3112's reset condition. The processor interface supplies the transmit clock by default. The user needs to access registers in the DS3112 and the CPLD to configure the board. To facilitate configuration, definition files that support the DS3112 reference design (DS3112.def, DS3112RD.def) can be downloaded from our website, www.maxim-ic.com/telecom. DS3150 INFORMATION For more information about the DS3150, please consult the DS3150 data sheet available on our website at www.maxim-ic.com/DS3150. Software downloads are also available for this demo kit. DS3112 INFORMATION For more information about the DS3112, please consult the DS3112 data sheet available on our website at www.maxim-ic.com/DS3112. Software downloads are also available for this demo kit. DK101/DK2000 INFORMATION For more information about the DK101 or DK2000, please consult the respective data sheets available on our website at www.maxim-ic.com/DK101 and www.maxim-ic.com/DK2000. TECHNICAL SUPPORT For additional technical support, please e-mail your questions to telecom.support@dalsemi.com. 4 of 11 |
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